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%\newcommand{\chapter}[1]{}
\newcommand{\targetm}{\xspace{\sc RISCV }\xspace{}} %% change !


\author{Équipe pédagogique IN330}
\date{2025-2026}
\title{\targetm ISA - Documentation pour le projet de IN330}

\begin{document}
\maketitle
\vspace{-55mm}
\includegraphics[width=3cm]{../../logos/logo_esisar.png}% \vspace*{5cm}\includegraphics{../logos/lyon1.jpg}
\vspace{3cm}
%%% INLINE


% \chapter{\targetm Assembly Documentation (ISA), rv64g}
% \label{app:targetm}

%\todo{2019 : à relire}

\paragraph{About}
\begin{itemize}
\item RISCV is an open instruction set initially developed by Berkeley
  University, used among others by Western Digital, Alibaba and
  Nvidia.
\item We are using the rv64g instruction set: \textbf{R}isc-\textbf{V},
  64 bits, \textbf{G}eneral purpose (base instruction set, and extensions
  for floating point, atomic and multiplications), without compressed
  instructions. In practice, we will use only 32 bits instructions
  (and 64 bits registers).

\item  The rest of the documentation is adapted from
\url{https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md}
and
\url{https://github.com/jameslzhu/riscv-card/blob/master/riscv-card.pdf}

\end{itemize}

\subsection*{Registers}

RISC-V defines
various types, depending on which extensions are included: The general
registers (with the program counter), control registers, floating point
registers (F extension), and vector registers (V extension). We won't
use control nor F or V registers.

\paragraph{General registers}
The RV64I base integer ISA includes 32 registers, named \texttt{x0} to
\texttt{x31}. Each register is a 64-bit integer and can be represented in a C program with a variable of type \texttt{int64\_t}. {\bf The program counter \texttt{PC}} is separate from these
registers, in contrast to other processors such as the ARM. The first
register, \texttt{x0}, has a special function: reading it always returns
0 and writes to it are ignored.

In practice, the programmer doesn't use this notation for the registers.
% Though \texttt{x1} to \texttt{x31} are all equally general-use registers
% as far as the processor is concerned, by convention certain registers
% are used for special tasks. 
In assembler, they are given standardized
names as part of the RISC-V \textbf{application binary interface} (ABI)~\footnote{In the official documentation these conventions are given}.
% This is what you will usually see in code listings. If you really want
% to see the numeric register names, the \texttt{-M} argument to objdump
% will provide them.
\ \\
{\small
  
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|c|}
  \hline
  Register & x0 & x1 &x2 & x3 & x4 & x5 & x6 & x7 & x8 & x9 & x10 & x11 & x12 & x13 & x14 & x15 \\
  \hline
  Alias & zero & ra & sp & gp & tp & t0 & t1 & t2 & s0 & s1 & a0 & a1 & a2 & a3 & a4 & a5\\
  \hline\hline
  Register & x16 & x17 & x18 & x19 & x20 & x21 & x22 & x23 & x24 & x25 & x26 & x27 & x28& x29 & x30 & x31 \\
  \hline
  Alias &  a6 & a7 & s2 & s3 & s4 & s5 & s6 & s7 & s8 & s9 & s10 & s11 & t3 & t4& t5 & t6\\
  \hline       
\end{tabular}
}


% \begin{longtable}[]{@{}
%   >{\raggedright\arraybackslash}p{(\columnwidth - 6\tabcolsep) * \real{0.2143}}
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%   >{\raggedright\arraybackslash}p{(\columnwidth - 6\tabcolsep) * \real{0.1429}}@{}}
% \toprule
% \begin{minipage}[b]{\linewidth}\raggedright
% Register
% \end{minipage} & \begin{minipage}[b]{\linewidth}\raggedright
% ABI
% \end{minipage} & \begin{minipage}[b]{\linewidth}\raggedright
% Use by convention
% \end{minipage} & \begin{minipage}[b]{\linewidth}\raggedright
% Preserved?
% \end{minipage} \\
% \midrule
% \endhead
% x0 & zero & hardwired to 0, ignores writes & \emph{n/a} \\
% x1 & ra & return address for jumps & no \\
% x2 & sp & stack pointer & yes \\
% x3 & gp & global pointer & \emph{n/a} \\
% x4 & tp & thread pointer & \emph{n/a} \\
% x5 & t0 & temporary register 0 & no \\
% x6 & t1 & temporary register 1 & no \\
% x7 & t2 & temporary register 2 & no \\
% x8 & s0 \emph{or} fp & saved register 0 \emph{or} frame pointer & yes \\
% x9 & s1 & saved register 1 & yes \\
% x10 & a0 & return value \emph{or} function argument 0 & no \\
% x11 & a1 & return value \emph{or} function argument 1 & no \\
% x12 & a2 & function argument 2 & no \\
% x13 & a3 & function argument 3 & no \\
% x14 & a4 & function argument 4 & no \\
% x15 & a5 & function argument 5 & no \\
% x16 & a6 & function argument 6 & no \\
% x17 & a7 & function argument 7 & no \\
% x18 & s2 & saved register 2 & yes \\
% x19 & s3 & saved register 3 & yes \\
% x20 & s4 & saved register 4 & yes \\
% x21 & s5 & saved register 5 & yes \\
% x22 & s6 & saved register 6 & yes \\
% x23 & s7 & saved register 6 & yes \\
% x24 & s8 & saved register 8 & yes \\
% x25 & s9 & saved register 9 & yes \\
% x26 & s10 & saved register 10 & yes \\
% x27 & s11 & saved register 11 & yes \\
% x28 & t3 & temporary register 3 & no \\
% x29 & t4 & temporary register 4 & no \\
% x30 & t5 & temporary register 5 & no \\
% x31 & t6 & temporary register 6 & no \\
% pc & \emph{(none)} & program counter & \emph{n/a} \\
% \bottomrule
% \end{longtable}

% \emph{Registers of the RV32I. Based on RISC-V documentation and
% Patterson and Waterman ``The RISC-V Reader'' (2017)}

%\input{riscv-asm-adapted.tex}

\subsection*{Instruction encoding}

All of the instructions listed here have a 32-bit encoding. They can be represented in a C program using a value of type \texttt{uint32\_t}.

%%%cf riscv-card.tex/base.tex
\newcommand{\instbit}[1]{\mbox{\scriptsize #1}}
\newcommand{\instbitrange}[2]{~\instbit{#1} \hfill \instbit{#2}~}


% New column types to use in tabular environment for instruction formats.
% Allocate 0.18in per bit.
% \newcolumntype{I}{>{\centering\arraybackslash}p{0.18in}}
% Two-bit centered column.
\newcolumntype{W}{>{\centering\arraybackslash}p{0.36in}}
% Three-bit centered column.
\newcolumntype{F}{>{\centering\arraybackslash}p{0.54in}}
% Four-bit centered column.
% \newcolumntype{Y}{>{\centering\arraybackslash}p{0.72in}}
% Five-bit centered column.
\newcolumntype{R}{>{\centering\arraybackslash}p{0.9in}}
% Six-bit centered column.
% \newcolumntype{S}{>{\centering\arraybackslash}p{1.08in}}
% Seven-bit centered column.
\newcolumntype{O}{>{\centering\arraybackslash}p{1.26in}}
% Typewriter font 
\newcolumntype{T}{>{\texttt\bgroup}l<{\egroup}}
% Typewriter font (code) 
\newcolumntype{C}{>{\texttt\bgroup}p{2.5in}<{\egroup}}


% \paragraph{Credit}

% This is a subset of the RISC-V greencard, by James Izhu, licence CC by SA,
% \url{https://github.com/jameslzhu/riscv-card}

\paragraph{Core Instruction Formats}

\small
\begin{center}
\begin{tabular}
{p{0in}p{0.4in}p{0.05in}p{0.05in}p{0.05in}p{0.05in}p{0.4in}p{0.6in}p{0.4in}p{0.6in}p{0.7in}l}
&
\multicolumn{1}{l}{\instbit{31}} &
\multicolumn{1}{r}{\instbit{27}} &
\instbit{26} &
\instbit{25} &
\multicolumn{1}{l}{\instbit{24}} &
\multicolumn{1}{r}{\instbit{20}} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\cline{2-11}

&
\multicolumn{4}{|c|}{funct7} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{funct3} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} & R-type \\
\cline{2-11}

&
\multicolumn{6}{|c|}{imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{funct3} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} & I-type \\
\cline{2-11}

&
\multicolumn{4}{|c|}{imm[11:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{funct3} &
\multicolumn{1}{c|}{imm[4:0]} &
\multicolumn{1}{c|}{opcode} & S-type \\
\cline{2-11}

&
\multicolumn{4}{|c|}{imm[12$\vert$10:5]} &
\multicolumn{2}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{funct3} &
\multicolumn{1}{c|}{imm[4:1$\vert$11]} &
\multicolumn{1}{c|}{opcode} & B-type \\
\cline{2-11}

% &
% \multicolumn{8}{|c|}{imm[31:12]} &
% \multicolumn{1}{c|}{rd} &
% \multicolumn{1}{c|}{opcode} & U-type \\
% \cline{2-11}

&
\multicolumn{8}{|c|}{imm[20$\vert$10:1$\vert$11$\vert$19:12]} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} & J-type \\
\cline{2-11}
\end{tabular}
\end{center}

\begin{itemize}
\item ``imm[x:y]'' means ``bits x to y from binary representation of
  imm''. ``imm[y$\vert$x]'' means ``bits y, then x of imm''. U-types
  are ommited.

\item Immediates are encoded in 2's complement.

\item In the J-type format the immediate encodes a signed offset in multiples of 2 bytes (from current PC)

 \item for B-type and J-type, imm[0] is always 0, thus removed from the encoding.
\end{itemize}
\paragraph{RV64I Base Integer Instructions - (excerpt for IN330)}
\ \\
{\small
\begin{tabular}
{T | l | c | T | T | T | T } \hline
\rm Inst & Syntax                    & format & \rm Opcode & \rm funct3 & \rm funct7 & \rm Description (C)          \\ \hline
add      & add rd, rs1, rs2                     & R   & 0110011    & 0x0    & 0x00   & rd = rs1 + rs2               \\
sub      & sub rd, rs1, rs2                     & R   & 0110011    & 0x0    & 0x20   & rd = rs1 - rs2               \\
% xor      & XOR                     & R   & 0110011    & 0x4    & 0x00   & rd = rs1 \^{} rs2            & \\
% or       & OR                      & R   & 0110011    & 0x6    & 0x00   & rd = rs1 | rs2               & \\
% and      & AND                     & R   & 0110011    & 0x7    & 0x00   & rd = rs1 \& rs2              & \\
% sll      & Shift Left Logical      & R   & 0110011    & 0x1    & 0x00   & rd = rs1 \verb|<<| rs2       & \\
% srl      & Shift Right Logical     & R   & 0110011    & 0x2    & 0x00   & rd = rs1 \verb|>>| rs2       & \\
% sra      & Shift Right Arith*      & R   & 0110011    & 0x3    & 0x20   & rd = rs1 \verb|>>| rs2       & msb-extends \\
% slt      & Set Less Than           & R   & 0110011    & 0x2    & 0x00       & rd = (rs1 < rs2)?1:0         & \\
% sltu     & Set Less Than (U)       & R   & 0110011    & 0x3    & 0x00       & rd = (rs1 < rs2)?1:0         & zero-extends \\ \hline
addi     & add rd, rs1, imm          & I   & 0010011    & 0x0    &        & rd = rs1 + imm               \\
% xori     & XOR Immediate           & I   & 0010011    & 0x4    &        & rd = rs1 \^{} imm            & \\
% ori      & OR Immediate            & I   & 0010011    & 0x6    &        & rd = rs1 | imm               & \\
% andi     & AND Immediate           & I   & 0010011    & 0x7    &        & rd = rs1 \& imm                                                                                                          & \\
% slli     & Shift Left Logical Imm  & I   & 0010011    & 0x1    & 0x00   & rd = rs1 \verb|<<| imm       & \\
% srli     & Shift Right Logical Imm & I   & 0010011    & 0x1    & 0x00   & rd = rs1 \verb|>>| imm       & \\
% srai     & Shift Right Arith Imm   & I   & 0010011    & 0x3    & 0x20   & rd = rs1 \verb|>>| imm       & msb-extends \\
% slti     & Set Less Than Imm       & I   & 0010011    & 0x2    &        & rd = (rs1 < imm)?1:0         & \\
% sltiu    & Set Less Than Imm (U)   & I   & 0010011    & 0x3    &        & rd = (rs1 < imm)?1:0         & zero-extends \\ \hline
%lb       & Load Byte               & I   & 0000011    & 0x0    &        & rd = M[rs1+imm][0:7]         & \\
%lh       & Load Half               & I   & 0000011    & 0x1    &        & rd = M[rs1+imm][0:15]        & \\
ld       & ld rd, imm(rs1)             & I   & 0000011    & 0x3    &        & rd = M[rs1+imm]       \\
% lbu      & Load Byte (U)           & I   & 0000011    & 0x4    &        & rd = M[rs1+imm][0:7]         & zero-extends \\
% lhu      & Load Half (U)           & I   & 0000011    & 0x5    &        & rd = M[rs1+imm][0:15]        & zero-extends \\ \hline
%sb       & Store Byte              & S   & 0100011    & 0x0    &        & M[rs1+imm][0:7]  = rs2[0:7]  & \\
%sh       & Store Half              & S   & 0100011    & 0x1    &        & M[rs1+imm][0:15] = rs2[0:15] & \\
sd       & sd rs2, imm(rs1)              & S   & 0100011    & 0x3    &        & M[rs1+imm] = rs2  \\ \hline
beq      & beq rs1,rs2, imm             & B   & 1100011    & 0x0    &        & if(rs1 == rs2) PC += imm      \\
bne      & bne rs1,rs2,imm               & B   & 1100011    & 0x1    &        & if(rs1 != rs2) PC += imm      \\
blt      & blt rs1,rs2,imm                & B   & 1100011    & 0x4    &        & if(rs1 < \enspace rs2) PC += imm  \\
bge      & bge rs1,rs2,imm           & B   & 1100011    & 0x5    &        & if(rs1 >= rs2) PC += imm     \\
% bltu     & Branch $<$ (U)            & B   & 1100011    & 0x6    &        & if(rs1 < \enspace rs2) PC += imm & zero-extends \\
% bgeu     & Branch $\geq$ (U)       & B   & 1100011    & 0x7    &        & if(rs1 >= rs2) PC += imm     & zero-extends \\ \hline
jal      & jal rd,imm           & J   & 1101111    &        &        & rd = PC+4; PC += imm         \\
% jalr     & Jump And Link Reg       & I   & 1100111    & 0x0    &        & rd = PC+4; PC = rs1 + imm    & \\ \hline
% lui      & Load Upper Imm          & U   & 0110111    &        &        & rd = imm \verb|<<| 12        & \\
% auipc    & Add Upper Imm to PC     & U   & 0010111    &        &        & rd = PC + (imm \verb|<<| 12) & \\ \hline
% ecall    & Environment Call        & I   & 1110011    & 0x0    & 0x00   & Transfer control to OS       & imm: 0x000 \\ \hline
% ebreak   & Environment Break       & I   & 1110011    & 0x0    & 0x00   & Transfer control to debugger & imm: 0x001 \\ \hline
\hline
\end{tabular}
}

\paragraph{Pseudo-instructions}\ \\
{\small
  \begin{tabular}{l| l |l}
    \hline
  Pseudoinstruction & Base Instruction(s) & Meaning \\
  \hline
{\tt j offset} & {\tt jal x0, offset} & Jump \\
{\tt li rd, imm} & {\tt addi rd, zero, imm} & Load immediate \\
    {\tt mv rd, rs} & {\tt addi rd, rs, 0} & Copy register \\
    \hline
\end{tabular}
}

(The \texttt{li} replacement is in reality a bit different).

%\input{riscv-card-subset.tex}


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